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65 nm

 

32-nm

 
  • ST, Synopsys partner to deliver complete design flow for 32-nm
    > IC Compiler Zroute
    > In May, a project between ST and Synopsys resulted in significantly improved verification of analog IC design, the companies then claimed. As a result the chip maker said it had adopted Synopsys' HSIM-XA for its next generation smart power devices targeting the automotive sector.
  • ARM, IBM Alliance tip 32nm-based processor with HK+MG
    > It is the first ever 32nm Cortex(TM) family processor core, built with ARM Physical IP, on a test chip from the IBM Common Platform in its 32nm High-K metal gate (HKMG) process.
    > This development follows nine months of collaboration between ARM and the Common Platform. The successful test chip demonstrates that the critical technologies are proven and is an important stepping stone towards implementing the Cortex-A9 and future processors at advanced process nodes.
  • Apache, ST to collaborate on 45-, 32-nm challenges
    > The deal expands ST's use of Apache's RedHawk and Sentinel platforms to address the upcoming design challenges such as 3D-IC power integrity, DDR jitter detection and prevention, chip-package-system convergence and EMI analysis, Apache said.
  • Mentor Graphics Olympus P&R and Calibre Verification Platforms Qualified for 32n...
    > The Olympus-SoC implementation platform was architected from the ground up to address the key challenges of physical design at 32nm. It provides native concurrent multi-corner multi-mode optimization, DFM-aware routing, automation for all low power design methodologies, 100M+ gate capacity, full multithreading, and the industry’s only parallel timing engine to deliver efficient scaling on multicore, multiprocessor computing platforms.
  • ST qualifies Mentor design-to-silicon platform
    > "STMicroelectronics has selected Mentor's design-to-silicon platform for its advanced capabilities that specifically target the challenges of 32nm and have a direct impact on our business. These challenges include the enormous complexity of new designs, the need for concurrent timing and power closure to reduce time-to-tapeout, and the ability to make designs resilient to variations in manufacturing," said Philippe Magarshack, STMicroelectronics Technology R&D Group Vice President and Central CAD and Design Solutions General Manager.
  • ST using Mentor Graphics sim for 32nm cell libraries
    > Mentor Graphics Corporation (NASDAQ:MENT) today announced that STMicroelectronics (NYSE:STM), a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications, has used the Mentor Graphics Eldo(R) circuit simulator to characterize its first CMOS 32nm cell libraries. The companies are long-term partners in the domain of advanced circuit simulation techniques for digital and analog IP characterization. This cooperation was recently brought to even higher levels, to ensure the successful development of a characterization flow optimized for the leading-edge CMOS 32nm high-K metal gate low power ISDA (International Semiconductor Development Alliance) process.
  • Mentor Graphics Eldo Simulator used by STMicroelectronics to Characterize 32nm C...
    > WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced that STMicroelectronics (NYSE:STM), a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications, has used the Mentor Graphics Eldo® circuit simulator to characterize its first CMOS 32nm cell libraries. The companies are long-term partners in the domain of advanced circuit simulation techniques for digital and analog IP characterization. This cooperation was recently brought to even higher levels, to ensure the successful development of a characterization flow optimized for the leading-edge CMOS 32nm high-K metal gate low power ISDA (International Semiconductor Development Alliance) process.

Synopsys

 
  • Synopsys Delivers Multicore Support With The Latest PrimeTime Release
    > This release also introduces new runtime optimizations, allowing design engineers to run faster full timing and signal integrity (SI) analysis on their large designs early in the implementation process, thus reducing costly design closure iterations. These improvements work in concert to deliver up to 2X faster runtime and have been confirmed on a suite of leading semiconductor companies' designs ranging in size from one million to 50 million instances.
    > "The latest PrimeTime release demonstrates how Synopsys' R&D continues to innovate and execute on our multicore initiative," said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "Through continuous R&D investment, we have addressed a key STA and SI analysis challenge for our customers - utilizing CPU cores across machines to accelerate runtime. Companies can now make more effective use of their existing compute server farms while having the flexibility to take advantage of the latest multicore hardware."

Interra Systems

 
  • Memory Design and Verification
    > Memory design and verification services are complimented by Interra's MC2, that provides ability to automate the memory design process for standard and embedded memories. MC2 is used as a platform for seamless migration to new semiconductor manufacturing processes. The platform is also being used for design and distribution of memories and ensuring the reuse of a base design over many generations of processes. Numerous users have also taken advantage of the platform to scale their memory designs to higher densities.

Packaging

 
  • Low-profile Fine-pitch Ball Grid Array (LFBGA)
    > In support of customer demand and the industry's trend toward smaller, more compact designs, NXP, Texas Instruments (TI), and Integrated Device Technology, Inc. (IDT) have agreed to source logic devices with the same functionality and pin-outs in space-saving, low-profile, fine-pitch ball grid array (LFBGA) packaging. This initiative marks the first implementation of BGA packaging in logic devices. Space-constrained devices such as wireless telephone systems, base stations, networking systems, memory modules, and handheld computers are ideal applications for logic devices in LFBGA packages.

Cadence Artist

 

Virage Logic

 
  • STAR™ Memory System
  • Intelli™ PHY+DLL
    > Virage Logic’s Intelli PHY+DLL is a flexible and advanced solution for DRAM Physical Layer Interfaces (PHY) for ASIC and SoC designers requiring high-performance from a memory interface using the least amount of area. The Intelli PHY+DLL supports standard SDRAM, and DDR SDRAM, as well as a wide variety of standards for each type, including single data rate JEDEC standard SDRAM and Mobile SDRAM, double data rate JEDEC standard DDR1/2, DDR2/3, DDR3, MobileSDR, MobileDDR, SDR, and GDDR DRAM. The PHY is designed for easy integration, and includes features such as DQS squelch.

Yield

 
  • Stratosphere Solutions Inc.
    > Our tools are built on a "solutions" approach to optimizing parametric yield and performance; an approach that connects manufacturing and design, empowers internal engineering experts and leverages existing equipment and design tool infrastructure. Our tools are used to accurately characterize process variations, extract the necessary process intelligence to optimize process parametric yields, model variations such that they are design flow relevant, and finally integrate these sophisticated models in the design flow.

DFT

 
  • Deep Chip survey results and DFT - believe John or Gary?
    > By John’s count, Synopsys DFT Compiler only has 50% of the scan insertion market. Gary Smith believes it’s more like 78%.
    > According to his respondents, Synopsys TetraMAX is used twice as much as Mentor FastScan! Gary Smith’s numbers say the exact opposite.
    > So what do I think? Well, I believe Gary Smith’s DFT Compiler number. I think fewer and fewer people are inserting scan after synthesis is complete, most now compile scan-ready as part of their synthesis flow. Scan stitching can be done also with the place & route tool in some cases. So about 80% seems right.

CHIPit

 
  • High-Speed ASIC Prototyping
    > As of December 18, 2009, Synopsys, Inc. has closed its acquisition of ProDesign's CHIPit business unit.
    > The CHIPit platforms (scalable up to 21 FPGAs) can handle capacities up to 28 M ASIC gates and run at system speeds of up to 200 MHz and based on this speed the best solution for pre-silicon software development.

Process Variation

 

synthesis optimization factor (0.92)


40 nm shrink process

 

Synthesis & Partitioning Strategy

 
  • A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping
    > One element of timing-based partitioning is the distribution of clocks. The skew of the multiple-FPGA systems comes from the combination of skews on the board and inside the FPGAs. When a clock is generated inside one FPGA and distributed to others, the board skew for each receiving FPGA has to be well balanced, otherwise it will cause hold-time violations. The loop-back structure such as the one in the following figure is necessary if the clock-generation FPGA also receives the same clock.
  • SCE-MI Standard

STMicroelecronics

 
  • STMicroelectronics Unveils Latest Advances in Design Methodologies at DAC 2009
    > In the DAC 2009 'Management Day' session, Philippe Magarshack, STMicroelectronics' General Manager of Central CAD & Design Solutions will present: '3-D Stacking: Opportunities and Trends for Consumer SoCs', which will discuss 3-D integration as a promising technology to extend the momentum of Moore's Law into the next decade, offering higher transistor density, faster interconnects, heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. However, 3-D integration isn't without challenges: the presentation discusses the need for a range of new capabilities including process technology, architectures, design methods and tools, and manufacturing-worthy test solutions to be developed before 3-D chips can be mass produced for consumer applications.
  • Ciranova PyCells Adopted by STMicroelectronics for 32 Nanometer Physical Design ...
    > PDKs are a fundamental enabler and vital ingredient in integrated circuit (IC) design; reduction in PDK generation cycle time contributes ultimately to shorter time to market. Ciranova PyCells complement ST’s already-existing interoperable PDK environments, by enabling faster support of a wide range of complex devices for multiple foundry processes across a myriad of third-party tools (technology rules & electrical models). PyCell Studio also integrates an efficient and user-friendly IDE (Integrated Development Environment).

SAIF

 

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