компасы
группы
авторы
компас
компасмастера
войти
Наука и технологии
в избранное
0
684
DDR Memory
cache design
ddr
ddr3
драм
fabless
memory
register file
synopsys
ruchip
на сайте с 28 мая 2008
Компасы автора
Содержание:
1
DDR Interface Design
2
Synopsys
3
DDR3 memory
4
DRAM
5
Register File Design
6
DDR2
7
Memory Hierarchy
8
17n Marinescu algorithm
9
DDR SDRAM Memory Controller
10
Mentor
11
Logic
12
DDR for HPC
13
Testing
14
DDR2 Interface
15
DFI, ARM
16
ARM DFI
Содержание:
1
DDR Interface Design
2
Synopsys
3
DDR3 memory
4
DRAM
5
Register File Design
6
DDR2
7
Memory Hierarchy
8
17n Marinescu algorithm
9
DDR SDRAM Memory Controller
10
Mentor
11
Logic
12
DDR for HPC
13
Testing
14
DDR2 Interface
15
DFI, ARM
16
ARM DFI
1
DDR Interface Design
Overview of Memory Types and DDR Interface Design Implementation
DDR PHY Interface Specification 2.0
2
Synopsys
DesignWare DDR3/DDR2/DDR Memory Interface IP Solutions
Synopsys DesignWare DDR3/2, DDR2/3-Lite, and DDR2/DDR IP
3
DDR3 memory
Going green with DDR3 memory
DDR3 Controllers Hit the Market for SoCs and FPGAs
Altera DDR3
Denali DDR3
> Denali First to Release Full DDR3 DIMM IP Solution
Virage DDR3
Xilinx DDR3
4
DRAM
Organizational Design Trade-Offs at the DRAM, Memory Bus, and ...
Basic System Level DRAM Design
Fully-buffered DIMM DRAMs suit memory-constrained design
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
Memory Design
New DRAM circuit design approach for gigabit-era DRAM
5
Register File Design
Register File Design and Memory Design
6
DDR2
Hardware and Layout Design Considerations for DDR2 SDRAM Memory ...
7
Memory Hierarchy
Memory Hierarchy
Introduction to Cache’s
8
17n Marinescu algorithm
Memory Testing
Testing word oriented embedded RAMs using built-in self test ...
Walking, marching and galloping patterns for memory tests
Using march tests to test SRAMs - IEEE Design & Test of Computers
9
DDR SDRAM Memory Controller
DDR SDRAM Memory Controller that supports the AMBA AHB interface
Simplescalar 3.0a memory controller and DRAM models
10
Mentor
Simplifying DDR
> Mentor’s New DDR Wizard
11
Logic
Cross-coupled inverters static random access memory
12
DDR for HPC
DDR Infiniband
> В частности, в СКИФ МГУ используется DDR Infiniband, который обеспечивает скорость 20 Гигабит в секунду. В наших новых блейд-системах используется QDR Infiniband со скоростью передачи данных 40 Гигабит в секунду.
13
Testing
The Verigy V93000 High-Speed Memory (HSM) Series
> Fastest memory ATE solution offers at-speed I/O and at-speed core test for high-speed devices
> Using the proven per-pin timing architecture of the V93000 platform, the HSM Series delivers the functionality to address the most demanding DRAM technologies, including DDR3, DDR4, XDR and GDDR, and provides the flexibility to address the requirements of future DRAM technologies to ensure your test investment is protected.
14
DDR2 Interface
15
DFI, ARM
ARM Announces PL342 ARM PrimeCell Low-Power DDR2 Dynamic Memory Controller
> The PL342 memory controller’s modular design enables it to be adapted for use with many types of dynamic memory. Future releases will add support for additional memory types to provide optimal solutions for current and planned CPU and GPU cores.
High Speed Interface
> DFI compliant PHY
> Multiple DDR standards supported
> Seamless interoperability between IP
> Low noise, high signal integrity
> Robust ESD enabling full speed designs
16
ARM DFI
Комментарии
Оставить комментарий
видимый только автору
Похожие компасы
Paul Zimmer
Search People
Lucene: The Open Source Search Engine
Comparables4
The World of Drum & Bass - первый D'n'B фестиваль в мире
Goldie – король D'n'B и Jungle
Drum and Bass и Drill and Bass
создать компас
Состоит в группах
Fabless IC Design
