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Bruce Jacob
http://www.ece.umd.edu/~blj/ University of Maryland Memory-Systems Research
cache design
ddr
fabless
memory
RTOS
ruchip
на сайте с 28 мая 2008
Компасы автора
Содержание:
1
Bruce Jacob
2
Ph.D. Theses
3
M.S. Theses:
Содержание:
1
Bruce Jacob
2
Ph.D. Theses
3
M.S. Theses:
1
Bruce Jacob
University of Maryland Memory-Systems Research
Keystone Professor
and
Director of Computer Engineering
2
Ph.D. Theses
Prefetching vs. the Memory System: Optimizations for Multi-core Server Platforms
Sadagopan Srinivasan
Investigates prefetching scheme for servers with respect to realistic memory systems. Real systems disable prefetching in server settings, suggesting that there is a fundamental disconnect between research and practice. This thesis shows that the disconnect is due to the use of simplistic memory models; experimental results suggest that using simplistic models can mis-predict the system performance by a factor of two.
Understanding and Optimizing High-Speed Serial Memory-System Protocols. (Intel)
Brinda Ganesh
Next-generation memory systems such as the Fully-Buffered DIMM use a system topology more akin to a computer network than a traditional memory bus. Data movement in these systems is complicated by the bus organization, making it essential to understand the implications when designing schedulers for these systems.
High-Speed Performance, Power, and Thermal Co-Simulation for SoC Design. (Intel)
Ankush Varma
Developing tools and methodologies for fast, accurate, high-level power and thermal modeling on SoCs. Exploring power/thermal modeling for MEMS, mixed-signal and digital SoC components, how these models can be built into high-level System Description Languages (such as SystemC), and how high-level power models can be made robust to low-level design decisions.
Disk Design-Space Exploration in Terms of System-Level Performance, Power, and E...
Nuengwong (Ohm) Tuaycharoen
SYSim is a full-system simulator that integrates Bochs, Wattch, DRAMsim, and DiskSim, boots Linux, and enables complete memory hierarchy studies in both performance and power consumption domains. With it, we investigate the system-level impacts of disk- and DRAM-system technologies such as DRAM capacity, disk caching, disk speed, etc.
myCACTI: A New Cache-Design Tool for Pipelined Nanometer Caches. (AMD)
Samuel Rodriguez
This dissertation shows that both CACTI and eCACTI still contain major limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and nanometer caches, especially pipelined designs. These limitations and flaws are discussed in detail. This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and, in addition, introduces major enhancements to the simulation framework.
The Effects of Out-of-Order Execution on the Memory System. (Intel)
Aamer Jaleel
Studies the deleterious effects of out-of-order execution. Common wisdom holds that bigger is better: to wit, the larger the instruction window, the better the performance. Numerous studies show this result, and, consequently, numerous other studies investigate low-cost ways to implement large instruction windows. This study shows that, once one includes a realistic model of the memory system, nearly all of those projected performance gains fail to materialize.
Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-C...
David Tawei Wang
An in-depth treatment of modern, power-limited, DRAM systems. The timing parameters tFAW and tRRD, introduced at the DDR2 generation of DDRx SDRAM, have a deleterious effect on system-level performance, significantly limiting sustainable bandwidth. The work characterizes the problem and provides a scheduling algorithm that offers a solution.
Modern DRAM Architectures. (Michigan Tech)
Brian Davis
This thesis examines a variety of modern DRAM architectures in the context of current desktop workstations. The DRAM examined (EDO, Burst EDO, SDRAM, DDR, DDR2, Rambus, ESDRAM, FCRAM, VCM) include those which are available today, as well as a number of architectures which are expected to come to market in the near future. (co-advised by Trevor Mudge)
3
M.S. Theses:
FBsim and the Fully Buffered DIMM Memory System Architecture. (Lutron)
Rami Nasr
TERPS: The Embedded Reliable Processing System. (General Dynamics Robotics Syste...
Amol Gole
Extended Split-Issue Mechanism in VLIW DSPs to Support SMT and Hardware-ISA Deco...
Bharath Iyer
RTOS-Based Dynamic Voltage Scaling. (U. Maryland Ph.D. 2006)
Nuengwong (Ohm) Tuaycharoen
Nanoprocessors: Configurable Hardware Accelerators for Embedded Systems. (Army R...
Lei Zong
Architectural Support for Embedded Operating Systems. (U. Maryland Ph.D. 2007)
Brinda Ganesh
In-Line Interrupt Handling and Lockup-Free TLBs. (U. Maryland Ph.D. 2005)
Aamer Jaleel
Hardware Support for Real-Time Operating Systems. (EVI Technology)
Paul Kohout
RTOS Performance and Energy Consumption Analysis Based on an Embedded System Tes...
Tiebing Zhang
An Evaluation of Embedded System Behavior Using Full-System Software Emulation. ...
Christopher Collins
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