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1001

The Most Important Patents in IC Design Industry

ruchip
на сайте с 28 мая 2008
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Patents

Some patents that we have to respect before starting our R&D:

Issued on November 4, 2008

 
  • 7,448,050
    ARM—Handling multiple interrupts in a data processing system utilising multiple operating systems.
  • 7,448,038
    Micron—Method for using filtering to load balance a loop of parallel processing elements.
  • 7,448,025
    Intel—Qualification of event detection by thread ID and thread privilege level.
  • 7,447,941
    HP—Error recovery systems and methods for execution data paths.
  • 7,447,887
    Hitachi—Multithread processor.
  • 7,447,886
    Freescale—System for expanded instruction encoding and method thereof.
  • 7,447,885
    ARM—Reading prediction outcomes within a branch prediction mechanism.
  • 7,447,884
    Toshiba—Multi-table branch prediction circuit for predicting a branch's target address based on the branch's delay slot instruction address.
  • 7,447,883
    ARM—Allocation of branch target cache resources in dependence upon program instructions within an instruction queue.
  • 7,447,882
    ARM—Context switching within a data processing system having a branch prediction mechanism.
  • 7,447,881
    Fujitsu—Branch prediction apparatus and method.
  • 7,447,879
    IBM—Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss.
  • 7,447,877
    Intel—Method and apparatus for converting memory instructions to prefetch operations during a thread switch window.
  • 7,447,876
    Seiko Epson—System and method for handling load and/or store operations in a superscalar microprocessor.
  • 7,447,873
    NVIDIA—Multithreaded SIMD parallel processor with loading of groups of threads.
  • 7,447,871
    ARM—Data access program instruction encoding.
  • 7,447,868
    IBM—Using vector processors to accelerate cache lookups.
  • 7,447,867
    Freescale—Non-intrusive address mapping having a modified address space identifier and circuitry therefor.
  • 7,447,844
    IBM—Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule.
  • 7,447,725
    IBM—Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units.
  • 7,446,773
    NVIDIA—Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler.

Issued on October 28, 2008

 
  • 7,444,639
    TI—Load balanced interrupt handling in an embedded symmetric multiprocessor system.
  • 7,444,634
    Sun—Method and apparatus for providing dynamic locks for global resources.
  • 7,444,630
    STMicro—Method and apparatus for changing microcode to be executed in a processor.
  • 7,444,547
    IBM—Method, system, and product for programming in a simultaneous multi-threaded processor environment.
  • 7,444,531
    Pact XPP—Methods and devices for treating and processing data.
  • 7,444,526
    IBM—Performance conserving method for reducing power consumption in a server system.
  • 7,444,525
    Sony/IBM/Toshiba—Methods and apparatus for reducing leakage current in a disabled SOI circuit.
  • 7,444,498
    IBM—Load lookahead prefetch for microprocessors.
  • 7,444,497
    Intel—Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support.
  • 7,444,495
    HP—Processor and programmable logic computing arrangement.
  • 7,444,493
    Intel—Address translation for input/output devices using hierarchical translation tables.
  • 7,444,492
    Toshiba—Processor, virtual memory system, and virtual storing method.
  • 7,444,488
    Infineon—Method and programmable unit for bit field shifting.
  • 7,444,481
    Teplin Application—Packet processor memory interface with memory conflict valve checking.
  • 7,444,473
    Sun—Speculative memory accesses in a proximity communication-based off-chip cache memory architecture.
  • 7,444,471
    Transmeta—Method and system for using external storage to amortize CPU cycle utilization.
  • 7,444,457
    Intel—Retrieving data blocks with reduced linear addresses.
  • 7,443,196
    Tabula—Configuration network for a configurable IC.

Issued on October 21, 2008

 

Issued on April 29, 2008

 
  • 7,367,026
    IBM—Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization.
  • 7,366,932
    STMicro—Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation.
  • 7,366,885
    AMD—Method for optimizing loop control of microcoded instructions.
  • 7,366,884
    Agere—Context switching system for a multi-thread execution pipeline loop and method of operation thereof.
  • 7,366,881
    Intel—Method and apparatus for staggering execution of an instruction.
  • 7,366,880
    Sun—Facilitating value prediction to support speculative program execution.
  • 7,366,879
    Intel—Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses.
  • 7,366,877
    IBM—Speculative instruction issue in a simultaneously multithreaded processor.
  • 7,366,876
    Analog Devices—Efficient emulation instruction dispatch based on instruction width.
  • 7,366,874
    Samsung—Apparatus and method for dispatching very long instruction word having variable length.
  • 7,366,873
    Cray—Indirectly addressed vector load-operate-store method and apparatus.

Issued on April 22, 2008

 
  • 7,363,625
    IBM—Method for changing a thread priority in a simultaneous multithread processor.
  • 7,363,476
    Intel—Method and apparatus to support an expanded register set.
  • 7,363,475
    Via—Managing registers in a processor to emulate a portion of a stack.
  • 7,363,474
    Intel—Method and apparatus for suspending execution of a thread until a specified memory access occurs.
  • 7,363,470
    AMD—System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor.
  • 7,363,469
    IBM—Method and system for on-demand scratch register renaming.
  • 7,363,468
    IBM—Load address dependency mechanism system and method in a high frequency, low power processor system.
  • 7,363,467
    Intel—Dependence-chain processing using trace descriptors having dependency descriptors.
  • 7,363,464
    Intel—Apparatus and method for reduction of processor power consumption.
  • 7,363,463
    Microsoft—Method and system for caching address translations from multiple address spaces in virtual machines.
  • 7,363,176
    ARM—Operating voltage determination for an integrated circuit.
  • 7,362,133
    Viciciv—Three dimensional integrated circuits.

Issued on April 15, 2008

 
  • 7,360,221
    Cray—Task swap out in a multithreaded environment.
  • 7,360,218
    IBM—System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval.
  • 7,360,203
    Infineon—Program tracing in a multithreaded processor.
  • 7,360,217
    ConSentry—Multi-threaded packet processing engine for stateful packet processing.
  • 7,360,069
    HP—Systems and methods for executing across at least one memory barrier employing speculative fills.
  • 7,360,064
    Cisco—Thread interleaving in a multithreaded embedded processor.
  • 7,360,063
    IBM—Method for SIMD-oriented management of register maps for map-based indirect register-file access.
  • 7,360,062
    IBM—Method and apparatus for selecting an instruction thread for processing in a multi-thread processor.
  • 7,360,061
    ARM—Program instruction decompression and compression techniques.
  • 7,360,058
    IBM—System and method for generating effective address.
  • 7,360,028
    Sun—Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol.

Issued on April 8, 2008

 
  • 7,356,810
    Transitive—Program code conversion for program code referring to variable size registers.
  • 7,356,675
    Renesas—Data processor.
  • 7,356,674
    HP—Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine.
  • 7,356,673
    IBM—System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form.
  • 7,356,670
    NXP—Data processing system.
  • 7,356,553
    ARM—Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements.

Issued on April 1, 2008

 
  • 7,353,411
    AT&T—Power efficiency in microprocessors using reduction of hamming distance between data value.
  • 7,353,370
    Intel—Method and apparatus for processing an event occurrence within a multithreaded processor.
  • 7,353,369
    NVIDIA—System and method for managing divergent threads in a SIMD architecture.
  • 7,353,367
    Microunity—System and software for catenated group shift instruction.
  • 7,353,365
    Intel—Implementing check instructions in each thread within a redundant multithreading environments.
  • 7,353,364
    Sun—Apparatus and method for sharing a functional unit execution resource among a plurality of functional units.
  • 7,353,363
    Microsystems—Patchable and/or programmable decode using predecode selection.
  • 7,353,362
    IBM—Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus.
  • 7,353,163
    Transitive—Exception handling method and apparatus for use in program code conversion

Issued on January 29, 2008

 
  • 7,325,228
    HP—Data speculation across a procedure call using an advanced load address table.
  • 7,325,221
    Sonics—Logic system with configurable interface.
  • 7,325,124
    IBM—System and method of execution of register pointer instructions ahead of instruction issue.
  • 7,325,123
    QST Holdings—Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements.
  • 7,325,102
    Sun—Mechanism and method for cache snoop filtering.
  • 7,325,083
    Arm Limited—Delivering data processing requests to a suspended operating system.
  • 7,324,421
    Adaptec—Method and apparatus for data bit align.

Issued on January 22, 2008

 
  • 7,321,989
    Aerospace Corp.—Simultaneously multithreaded processing and single event failure detection method.
  • 7,321,965
    MIPS—Integrated mechanism for suspension and deallocation of computational threads of execution in a processor.
  • 7,321,964
    AMD—Store-to-load forwarding buffer using indexed lookup.
  • 7,321,963
    Intel—System and method for storing immediate data.
  • 7,321,910
    IP-First—Microprocessor apparatus and method for performing block cipher cryptographic functions.

Issued on January 15, 2008

 
  • 7,320,121
    SAS—Computer-implemented system and method for generating embedded code to add functionality to a user application.
  • 7,320,066
    Fujitsu—Branch predicting apparatus and branch predicting method.
  • 7,320,065
    Eleven Engineering—Multithread embedded processor with input/output capability.
  • 7,320,064
    Honeywell—Reconfigurable computing architecture for space applications.
  • 7,320,063
    Sun—Synchronization primitives for flexible scheduling of functional unit operations.
  • 7,320,062
    QST Holdings—Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  • 7,320,043
    Avocent—Split computer architecture to separate user and processor while retaining original user interface.
  • 7,320,013
    Adaptec—Method and apparatus for aligning operands for a processor.
  • 7,319,702
    Broadcom—Apparatus and method to receive and decode incoming data and to handle repeated simultaneous small fragments.

Issued on January 8, 2008

 
  • 7,318,169
    Fault tolerant computer.
  • 7,318,145
    MIPS—Random slip generator.
  • 7,318,144
    Cloudshield—Apparatus and method for interconnecting a processor to co-processors using shared memory.
  • 7,318,143
    ARM/U. of Michigan—Reuseable configuration data.
  • 7,318,126
    IBM—Asynchronous symmetric multiprocessing.
  • 7,317,755
    Via—Predicted parallel branch slicer and slicing method thereof.
  • 7,317,605
    IBM—Method and apparatus for improving performance margin in logic paths.
  • 7,317,331
    Tabula—Reconfigurable IC that has sections running at different reconfiguration rates.

Issued on January 1, 2008

 
  • 7,316,021
    Sun—Switching method in a multi-threaded processor.
  • 7,316,012
    Intel—System, method, and apparatus for spilling and filling rotating registers in software-pipelined loops.
  • 7,315,957
    NVIDIA—Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock.
  • 7,315,937
    MIPS—Microprocessor instructions for efficient bit stream extractions.
  • 7,315,935
    AMD—Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots.
  • 7,315,933
    Fujitsu—Re-configurable circuit and configuration switching method.
  • 7,315,932
    Data processing system having instruction specifiers for SIMD register operands and method thereof.
  • 7,315,921
    IP-First—Apparatus and method for selective memory attribute control.
  • 7,314,174
    Xilinx—Method and system for configuring an integrated circuit.

Issued on November 27, 2007

 
  • 7,302,627
    MIMAR TIBET—Apparatus for efficient LFSR calculation in a SIMD processor.
  • 7,302,597
    AT&T—Microprocessors with improved efficiency processing a variant signed magnitude format.
  • 7,302,557
    Impact—Method and apparatus for modulo scheduled loop execution in a processor architecture.
  • 7,302,556
    IBM—Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors.
  • 7,302,555
    Philips—Zero overhead branching and looping in time stationary processors.
  • 7,302,554
    Sony—Methods and apparatus for multi-processor pipeline parallelism.
  • 7,302,552
    Arm—System for processing VLIW words containing variable length instructions having embedded instruction length identifiers.
  • 7,302,551
    IP-First—Suppression of store checking.
  • 7,302,543
    NEC—Compressed memory architecture for embedded systems.
  • 7,302,532
    EMC Corporation—Central processing unit.
  • 7,302,527
    IBM—Systems and methods for executing load instructions that avoid order violations.
  • 7,302,504
    Altera—Methods and apparatus for providing data transfer control.
  • 7,302,503
    Broadcom—Memory access engine having multi-level command structure.
  • 7,302,462
    Mercury—Framework and methods for dynamic execution of digital data processor resources.
  • 7,301,541
    Microunity—Programmable processor and method with wide operations.
  • 7,301,368
    Tabula—Embedding memory within tile arrangement of a configurable IC.

Issued on November 20, 2007

 
  • 7,299,343
    VeriSilicon—System and method for cooperative execution of multiple branching instructions in a processor.
  • 7,299,342
    Coresonic—Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement.
  • 7,299,339
    Boeing—Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework.
  • 7,299,155
    Sonics—Method and apparatus for decomposing and verifying configurable hardware.
  • 7,298,169
    Tabula—Hybrid logic/interconnect circuit in a configurable IC.

Issued on November 13, 2007

 
  • 7,296,259
    Agere—Processor system with cache-based software breakpoints.
  • 7,296,175
    IBM—System on a chip bus with automatic pipeline stage insertion for timing closure.
  • 7,296,141
    Broadcom—Method for cancelling speculative conditional delay slot instructions.
  • 7,296,139
    NVIDIA—In-memory table structure for virtual address translation system with translation units of variable range size.
  • 7,296,137
    Freescale—Memory management circuitry translation information retrieval during debugging.
  • 7,295,037
    Tabula—Configurable IC with routing circuits with offset connections.

Issued on November 6, 2007

 
  • 7,293,163
    Sun—Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency.
  • 7,293,161
    Sun—Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode.
  • 7,293,160
    Sun—Mechanism for eliminating the restart penalty when reissuing deferred instructions.
  • 7,293,159
    IBM—Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder.
  • 7,293,141
    AMD—Cache word of interest latency organization.
  • 7,293,056
    Intel—Variable width, at least six-way addition/ accumulation instructions.

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