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322

Patent Watch Issued on February

ruchip
на сайте с 28 мая 2008
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Issued on February 24, 2009

 
  • 7,496,966
    AMD —Method and apparatus for controlling operation of a secure execution mode-capable processor in system management mode.
  • 7,496,917
    IBM —Virtual devices using a pluarlity of processors.
  • 7,496,902
    IBM —Data and instruction address compression.
  • 7,496,879
    Tabula —Concurrent optimization of physical design and operational cycle assignment.
  • 7,496,735
    Strandera —Method and apparatus for incremental commitment to architectural state in a microprocessor.
  • 7,496,734
    STMicro —System and method for handling register dependency in a stack-based pipelined processor.
  • 7,496,733
    IBM —System and method of execution of register pointer instructions ahead of instruction issues.
  • 7,496,732
    Intel —Method and apparatus for results speculation under run-ahead execution.
  • 7,496,721
    Teplin —Packet processor memory interface with late order binding.
  • 7,496,716
    Sun —Methods and apparatus to implement parallel transactions.
  • 7,496,673
    IBM —SIMD-RISC microprocessor architecture.
  • 7,496,494
    IBM —Method and system for multiprocessor emulation on a multiprocessor host system.

Issued on February 17, 2009

 
  • 7,493,615
    Sun—Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
  • 7,493,607
    BlueRISC—Statically speculative compilation and execution.
  • 7,493,600
    Faraday—Method for verifying branch prediction mechanism and accessible recording medium for storing program thereof.
  • 7,493,516
    Searete—Hardware-error tolerant computing.
  • 7,493,481
    NetXen—Direct hardware processing of internal data structure fields.
  • 7,493,480
    IBM—Method and apparatus for prefetching branch history information.
  • 7,493,479
    Renesas—Method and apparatus for event detection for multiple instruction-set processor.
  • 7,493,478
    IBM—Enhanced processor virtualization mechanism via saving and restoring soft processor/system states.
  • 7,493,475
    STMicro—Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address.
  • 7,493,474
    Altera—Methods and apparatus for transforming, loading, and executing super-set instructions.
  • 7,493,473
    STMicro—Method of executing instructions using first and second control units that share a state register.
  • 7,493,472
    Ricoh—Meta-address architecture for parallel, dynamically reconfigurable computing.
  • 7,493,471
    Sun—Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready.
  • 7,493,470
    ARC—Processor apparatus and methods optimized for control applications.
  • 7,493,468
    IBM—Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing.
  • 7,493,451
    P.A. Semi—Prefetch unit.
  • 7,493,417
    IBM—Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system.
  • 7,493,375
    QST—Storage and delivery of device features.
  • 7,492,186
    Tabula—Runtime loading of configuration data in a configurable IC.

Issued on February 10, 2009

 
  • 7,490,254
    AMD—Increasing workload performance of one or more cores on multiple core processors.
  • 7,490,230
    MIPS—Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor.
  • 7,490,229
    Sun—Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution.
  • 7,490,226
    IBM—Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor.
  • 7,490,225
    Sun—Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number.
  • 7,490,223
    Sun—Dynamic resource allocation among master processors that require service from a coprocessor.
  • 7,490,221
    ARM—Synchronization between pipelines in a data processing apparatus utilizing a synchronization queue.
  • 7,490,219
    Fujitsu—Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors.
  • 7,490,218
    U. Washington—Building a wavecache.
  • 7,490,217
    IBM—Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables.
  • 7,490,210
    Micron —System and method for processor with predictive memory retrieval assist.
  • 7,490,117
    Intel—Dynamic performance monitoring-based approach to memory management.
  • 7,490,110
    IBM—Predictable query execution through early materialization.
  • 7,489,752
    ARM —Synchronisation of signals between asynchronous logic.
  • 7,489,162
    Tabula—Users registers in a reconfigurable IC.
  • 7,487,505
    Intel—Multithreaded microprocessor with register allocation based on number of active threads.
  • 7,487,502
    Intel—Programmable event driven yield mechanism which may activate other threads.
  • 7,487,496
    IBM—Computer program functional partitioning method for heterogeneous multi-processing systems.
  • 7,487,398
    Intel—Microprocessor design support for computer system and platform validation.
  • 7,487,374
    IBM—Dynamic power and clock-gating method and circuitry with sleep mode based on estimated time for receipt of next wake-up signal.
  • 7,487,369
    RMI—Low-power cache system and method.
  • 7,487,340
    IBM—Local and global branch prediction information storage.
  • 7,487,338
    Renesas—Data processor for modifying and executing operation of instruction code according to the indication of other instruction code.
  • 7,487,337
    Intel—Back-end renaming in a continual flow processor pipeline.
  • 7,487,335
    Sun—Method and apparatus for accessing registers during deferred execution.
  • 7,487,333
    Seiko Epson—High-performance, superscalar-based computer system with out-of-order instruction execution.
  • 7,487,317
    Sun—Cache-aware scheduling for a chip multithreading processor.
  • 7,487,304
    Teplin—Packet processor memory interface with active packet list.
  • 7,487,300
    NXP—Data processing circuit with multiplexed memory.
  • 7,487,296
    Sun—Multi-stride prefetcher with a recurring prefetch table.

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