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350

Patent Watch Issued on March

ruchip
на сайте с 28 мая 2008
Компасы автора
 

Issued on March 31, 2009

 
  • 7,512,772
    AMD — Soft error handling in microprocessors.
  • 7,512,740
    MIPS — Microprocessor with improved data stream prefetching.
  • 7,512,728
    Axis — Inter-chip communication system.
  • 7,512,724
    US Navy — Multi-thread peripheral processing using dedicated peripheral bus.

Issued on March 24, 2009

 
  • 7,509,643
    Sun — Method and apparatus for supporting asymmetric multi-threading in a computer system.
  • 7,509,619
    Xilinx — Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages
  • 7,509,512
    National Semi — Instruction-initiated method for suspending operation of a pipelined data processor
  • 7,509,486
    Broadcom — Encryption processor for performing accelerated computations to establish secure network sessions connections
  • 7,509,484
    Sun — Handling cache misses by selectively flushing the pipeline
  • 7,509,481
    Sun — Patchable and/or programmable pre-decode
  • 7,509,480
    MIPS — Selection of ISA decoding mode for plural instruction sets based upon instruction address
  • 7,509,459
    MIPS — Microprocessor with improved data stream prefetching
  • 7,509,447
    MIPS — Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor.
  • 7,509,391
    TI — Unified memory management system for multi processor heterogeneous architecture.
  • 7,509,367
    Intel — Method and apparatus for performing multiply-add operations on packed data.
  • 7,509,366
    Microunity — Multiplier array processing system with enhanced utilization at lower precision.
  • 7,509,365
    IBM — Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units.
  • 7,509,142
    none — Notebook computer with replaceable battery unit.
  • 7,508,981
    Samsung — Dual layer bus architecture for system-on-a-chip.
  • 7,508,328
    Nemochips — Entropy processor for decoding.

Issued on March 17, 2009

 
  • 7,506,326
    IBM — Method and apparatus for choosing register classes and/or instruction categories.
  • 7,506,185
    Seiko Epson — Selective power-down for high performance CPU/system.
  • 7,506,140
    MIPS — Return data selector employing barrel-incrementer-based round-robin apparatus.
  • 7,506,139
    IBM — Method and apparatus for register renaming using multiple physical register files and avoiding associative search.
  • 7,506,137
    Altera — Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions.
  • 7,506,135
    none — Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements.
  • 7,506,131
    TI — Reformat logic to translate between a virtual address and a compressed physical address.
  • 7,506,106
    MIPS — Microprocessor with improved data stream prefetching.
  • 7,506,104
    Teplin — Packet processor memory interface with speculative memory reads.
  • 7,505,822
    U. of Maryland — Optical interconnect structure in a computer system and method of transporting data between processing elements and memory through the optical interconnect structure.
  • 7,504,858
    Tabula — Configurable integrated circuit with parallel non-neighboring offset connections.
  • 7,504,851
    Achronix — Fault tolerant asynchronous circuits.

Issued on March 10, 2009

 
  • 7,502,943
    Via — Microprocessor apparatus and method for providing configurable cryptographic block cipher round results.
  • 7,502,917
    IBM — High speed memory cloning facility via a lockless multiprocessor mechanism.
  • 7,502,915
    NVIDIA — System and method using embedded microprocessor as a node in an adaptable computing machine.
  • 7,502,913
    Microsoft — Switch prefetch in a multicore computer chip.
  • 7,502,911
    QUALCOMM — Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length.
  • 7,502,910
    Sun — Sideband scout thread processor for reducing latency associated with a main processor.
  • 7,502,896
    STMicro — System and method for maintaining the integrity of data transfers in shared memory configurations.
  • 7,502,892
    Intel — Decoupling request for ownership tag reads from data read operations.
  • 7,502,880
    Via — Apparatus and method for quad-pumped address bus.
  • 7,502,725
    IBM — Method, system and computer program product for register management in a simulation environment.

Issued on March 3, 2009

 
  • 7,500,240
    Intel — Apparatus and method for scheduling threads in multi-threading processors.
  • 7,500,126
    NXP — Arrangement and method for controlling power modes of hardware resources.
  • 7,500,119
    Intel — Power saving techniques for use in communication systems, networks, and devices.
  • 7,500,088
    Sony — Methods and apparatus for updating of a branch history table.
  • 7,500,087
    Intel — Synchronization of parallel processes using speculative execution of synchronization instructions.
  • 7,500,086
    Sun — Start transactional execution (STE) instruction to support transactional program execution.
  • 7,500,084
    IBM — Multifunction hexadecimal instruction form.
  • 7,500,060
    Xilinx — Hardware stack structure using programmable logic.
  • 7,500,035
    IBM — Livelock resolution method.

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