Patent Watch Issued on September

на сайте с 28 мая 2008

7,430,742
Micron—Method for load balancing a line of parallel processing elements.
7,430,737
Sun—Processor and method for supporting compiler directed multithreading management.
7,430,678
Matsushita—Low power operation control unit and program optimizing method.
7,430,657
Intel—System, method and device for queuing branch predictions.
7,430,655
Microunity—Method and software for multithreaded processor with partitioned operations
7,430,654
Via—Dynamic instruction dependency monitor and control system.
7,430,653
Sun—Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking.
7,430,651
Seiko-Epson—System and method for assigning tags to control instruction processing in a superscalar processor.
7,430,643
Sun—Multiple contexts for efficient use of translation lookaside buffer.
7,430,631
NXP—Access to a wide memory.
7,430,578
Intel—Method and apparatus for performing multiply-add operations on packed byte data.
7,430,574
Intel—Efficient execution and emulation of bit scan operations.
7,430,573
Seiko Epson—Processor.
7,429,870
Element CXI—Resilient integrated circuit architecture.

7,428,727
Cray—Debugging techniques in a multithreaded environment.
7,428,721
Tabula—Operational cycle assignment in a configurable IC.
7,428,653
Mindspeed—Method and system for execution and latching of data in alternate threads
7,428,632
ARM—Branch prediction mechanism using a branch cache memory and an extended pattern cache.
7,428,631
Intel—Apparatus and method using different size rename registers for partial-bit and bulk-bit writes.
7,428,630
Altera Corporation—Processor adapted to receive different instruction sets.
7,428,627
Intel—Method and apparatus for predicting values in a processor having a plurality of prediction modes.
7,428,626
Microsoft—Method and system for a second level address translation in a virtual machine environment.
7,427,871
Element CXI—Fault tolerant integrated circuit architecture.

RE40509
Altera—Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture.
7,426,732
Cray—Placing a task of a multithreaded environment in a known state.
7,426,722
Transitive—Program code conversion for program code referring to variable size registers.
7,426,656
HP—Method and system executing user programs on non-deterministic processors.
7,426,648
Intel—Global and pseudo power state management for multiple processing elements.
7,426,631
IBM—Methods and systems for storing branch information in an address table of a processor.
7,426,629
ARM—Processing activity masking in a data processing system.
7,426,627
Microsoft—Selective address translation for a resource such as a hardware device.
7,426,626
QUALCOMM—TLB lock indicator.
7,425,841
Tabula—Configurable circuits, IC's, and systems.

RE40498
Matsushita—Variable address length compiler and processor improved in address management.
7,424,622
Toshiba—Microprocessor with improved task management and table management mechanism.
7,424,601
—Methods and systems for running multiple operating systems in a single mobile device.
7,424,600
Matsushita—Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency.
7,424,599
MIPS—Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor.
7,424,598
Renesas—Data processor.
7,424,594
Altera—Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture.
7,424,591
IBM—Splash tables: an efficient hash scheme for processors.
7,424,579
Intel—Memory controller for processor having multiple multithreaded programmable units.
7,424,576
Intel—Parallel cachelets.
7,424,571
Gigafin—Array machine context data memory.
7,424,506
Durham Logistics—Architecture and related methods for efficiently performing complex arithmetic.
7,424,505
Intel—Method and apparatus for performing multiply-add operations on packed data.
7,424,501
Intel—Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations.
7,424,474
Altera—Data structure and method for sorting using heap-supernodes.
7,424,328
—Apparatus and method for wireless process control.

7,421,694
Microsoft—Systems and methods for enhancing performance of a coprocessor.
7,421,686
Transitive—Program code conversion.
7,421,595
STMicro—Device and method for managing a standby state of a microprocessor.
7,421,572
Intel—Branch instruction for processor with branching dependent on a specified bit in a register.
7,421,571
Intel—Apparatus and method for switching threads in multi-threading processors.
7,421,568
QUALCOMM—Power saving methods and apparatus to selectively enable cache bits based on known processor state.
7,421,566
IBM—Implementing instruction set architectures with non-contiguous register file specifiers.
7,421,565
Cray—Method and apparatus for indirectly addressed vector load-add -store across multi-processors.
7,421,561
Stretch—Instruction set for efficient bit stream and byte stream I/O.
7,421,544
Sun—Facilitating concurrent non-transactional execution in a transactional memory system.
7,420,390
Altera—Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size.
7,420,389
Tabula—Clock distribution in a configurable IC.

Оставить комментарий

видимый только автору